Date of Graduation
Master of Science in Electrical Engineering (MSEE)
H. Alan Mantooth
Simon S. Ang
Second Committee Member
Roy A. McCann
This thesis presents the design, simulation and layout of a silicon carbide (SiC) 8 bit split array charge scaling digital to analog convertor (DAC). The converter consists of the charge scaling capacitor chain with two operational trans-conductance amplifiers (op amp) in voltage follower configuration. The op amps used in the design have the input common mode ranges of 0 to 11.2 V and 4.7V to 14.5V respectively. Additional logic circuit topologies are designed, which help to switch the op amps when needed to provide a rail to rail unity gain at the output. As the design is based on the charge based approach it has the advantages of low power dissipation (capacitor array does not dissipate DC power), the output is sampled and held and the almost zero offset. The specification of the DAC is (1) power operation less than 200 mW (2) operation up to 1 MHz and (3) with a reset enables, to reset the converter when needed. The main focus of the thesis is on the monotonicity and to reduce capacitor sizes. The size of the largest capacitor used in the design is 16pF which makes the design as compact as possible. The major area of application of this convertor is at high temperature applications where the silicon based integrated circuits(IC) fail to operate properly.
Akula, Sai Kiran, "8 Bit Split Array Based Charge Scaling Digital to Analog Converter with Rail to Rail Buffered Output" (2015). Theses and Dissertations. 1393.