Date of Graduation

12-2011

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Degree Level

Graduate

Department

Electrical Engineering

Advisor

Alan H. Mantooth

Committee Member

Roy A. McCann

Second Committee Member

Jingxian Wu

Keywords

Communication and the arts; Applied sciences; Charge pump; Closed loop; Frequency synthesizer; Phase locked loop; Pll; Tristate phase frequency detector

Abstract

There is a strong need for stable frequency references with large tuning ranges in today's communication systems. While the crystal oscillators assure good frequency stability, it is not possible to achieve a large frequency range by tuning the passive components attached to them. Frequency synthesizers are usually used for this purpose because of their ability to produce a variety of output frequencies. The Phase Locked Loop (PLL) based frequency synthesizer is the most preferred of all types of synthesizers available because of its additional features like programmability, low noise and low cost as well as high accuracy and stability. The main idea of this PLL-based synthesizer is to phase-lock its output signal with an input reference signal and to produce a synchronous output. It does this by generating an error signal to correct the oscillator frequency. This functionality is achieved by integrating a phase detector, charge pump, loop filter and voltage controlled oscillator block in series with a frequency divider in feedback. This thesis presents, in detail, the design of all the individual PLL blocks, the strategies employed in the design, issues faced in testing and the test data from simulation and measurement. All the above mentioned PLL blocks are designed in the 130 nm IBM-CMOS cmrf8sf process and optimized for low power consumption. PLLs are used in almost all kinds of communication systems, transmitters and receivers for applications such as carrier recovery, carrier generation, clock slew correction, frequency modulation and demodulation.

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