Date of Graduation

8-2013

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering (MSCmpE)

Degree Level

Graduate

Department

Computer Science & Computer Engineering

Advisor

Jia Di

Committee Member

Dale R. Thompson

Second Committee Member

Scott C. Smith

Abstract

Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits are more energy efficient for any size provided the number of pipeline stages does not become too great. Otherwise NCL would consume less energy. A combinational logic gate count to register gate count ratio of 3 was given to help determine when an MTNCL circuit would have too many pipeline stages for circuits designed with IBM's 130nm 8RF-DM design kit.

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