Document Type

Patent

Publication Date

1-15-2002

Abstract

A low temperature process for forming a metal doped silicon layer in which an amorphous silicon layer is deposited onto a substrate at low temperatures, with a metal layer then deposited upon the silicon layer is described. This structure is then annealed at low temperatures to form a metal doped polycrystalline silicon having greater than about 1x10^20 dopant atoms per cubic cm of silicon.

Department

Electrical Engineering

Patent Number

US6339013

Application Filed

5-13-1997

Assignee

Board of Trustees of the University of Arkansas (Little Rock, AR)

Comments

Hameed A. Naseem, Department of Electrical Engineering; M. Shahidul Haque, Department of Electrical Engineering; William D. Brown, Department of Electrical Engineering

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