Document Type

Patent

Publication Date

6-26-2012

Abstract

A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) is described. The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. This circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Department

Computer Science and Computer Engineering; Electrical Engineering

Patent Number

US8207758

Application Number

US20120133390

Application Published

5-31-2012

Application Filed

7-1-2011

Assignee

Board of Trustees of the University of Arkansas (Little Rock, AR)

Comments

Jia Di, Department of Computer Science and Computer Engineering; Scott C. Smith, Department of Electrical Engineering

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