Asynchronous Parallel Platforms with Balanced Performance and Energy

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Article - Abstract Only

Publication Date



Asynchronous circuit, DVS, Energy efficiency, Null cycle reduction, Parallel architecture


The landscape for digital integrated circuit design has changed from the one driven by performance to the one driven by energy or more-balanced design goals. Without the clock-related issues, asynchronous circuits enable further design tradeoffs and in-operation adaptive adjustments for energy efficiency. This paper presents a parallel homogeneous platform and a scalable heterogeneous platform implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction. Datapath control logic with NULL cycle reduction and arbitration network is incorporated in the heterogeneous platform. The platforms have been integrated with the data processing units using the IBM 130 nm 8RF process. Results show that the adaptive DVS mechanism is effective in balancing the energy and performance in both platforms.


Principal Investigator: Jia Di

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