Date of Graduation
5-2025
Document Type
Thesis
Degree Name
Bachelor of Science in Computer Engineering
Degree Level
Undergraduate
Department
Computer Science and Computer Engineering
Advisor/Mentor
Di, Jia
Committee Member
Andrews, David
Second Committee Member
Nelson, Alexander
Abstract
This thesis describes the creation of component libraries for the implementation of Multi-Threshold NULL Convention Logic (MTNCL) and Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) on AMD 7 Series, AMD UltraScale, and AMD UltraScale+ FPGAs. The utilization of these libraries is identical to those used in the creation of MTNCL and MTD3L application-specific integrated circuits (ASICs), leading to intuitive use for designers familiar with the logic paradigms. Single-stage and pipelined designs were created using both libraries, which were then tested and verified to be logically equivalent to their ASIC counterparts. Future work will include creating and testing a variety of designs, along with the creation of an open-source repository on GitHub.
Keywords
FPGA; MTNCL; MTD3L; quasi-delay-insensitive asynchronous logic; Vivado; edge computing
Citation
Harvey, K. T. (2025). An Approach of Implementing MTNCL and MTD3L Asynchronous Logic Paradigms on FPGAs. Electrical Engineering and Computer Science Undergraduate Honors Theses Retrieved from https://scholarworks.uark.edu/elcsuht/22
