Date of Graduation

5-2025

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering (MSCmpE)

Degree Level

Graduate

Department

Electrical Engineering and Computer Science

Advisor/Mentor

Di, Jia

Committee Member

Nelson, Alexander H.

Second Committee Member

Dix, Jeff

Keywords

Bus-Based; Chiplets; GALS; MTNCL; NCL; Pseudo-Crossbar

Abstract

System-on-Chip (SoC) complexity continues to present challenges in global clock distribution and power management. The Globally Asynchronous Locally Synchronous (GALS) approach addresses these issues by enabling asynchronous communication between locally synchronous chiplets. This thesis details the design and implementation of two GALS architectures employing asynchronous handshaking protocols through Multi-Threshold CMOS NULL Convention Logic (MTNCL). The first architecture, a pseudo-crossbar, uses arbiters and multiplexers/demultiplexers (MUX/DEMUX) for prioritized and dynamic communication between chiplets. The second, a bus-based approach, employs D-latches to manage communication sequentially with predetermined interrupts. This research explores the detailed implementation, functional distinctions, scalability, and integration trade-offs inherent to each design. The insights gained provide practical guidance for future advancements in embedded asynchronous communication system.

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