Date of Graduation

5-2025

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering (MSCmpE)

Degree Level

Graduate

Department

Electrical Engineering and Computer Science

Advisor/Mentor

Di, Jia

Committee Member

Nelson, Alexander H.

Second Committee Member

Dix, Jeff

Keywords

Integrated Circuit Design; Multi-Threshold NULL Convention Logic; Polymorphic Circuitry; Watermarking

Abstract

With the increasing demand for new state-of-the-art integrated circuits (ICs), intellectual property (IP) reuse has become more commonplace to both accelerate the design process and lessen the non-recurring engineering costs of a design. Reuseable IP poses significant security risks, not only to the creator of the IP, but also to the consumer purchasing the IP. For an IP vendor, this risk can come from illegal distribution, cloning, or overuse. For the purchaser, counterfeit IPs may be purchased from an unvetted vendor, leading to a substandard design, malfunctions, IP infringement, or security vulnerabilities. Hardware watermarking is a method to protect designers on both ends of a third-party IP purchase by either preventing misuse or proving that it occurred, as well as ensuring that the design has not been altered. For asynchronous Multi-Threshold NULL Convention Logic (MTNCL) circuits, a polymorphic watermarking scheme can provide proof of ownership that limits overhead on both the effort of insertion as well as the increase in area that comes from embedding additional circuitry. The objective of this thesis research is to explore the feasibility and benefits of using polymorphic gates to introduce a layer of security to a design by embedding a signature that can protect against IP misuse.

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