Date of Graduation

5-2025

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Degree Level

Graduate

Department

Electrical Engineering and Computer Science

Advisor/Mentor

Dix, Jeff

Committee Member

Chen, Zhong

Second Committee Member

Song, Xiaoqing

Keywords

power; low dropout regulator; circuits

Abstract

Modern ICs require the use of multiple voltage regulators to regulate power, this creates the need for analog low dropout regulator (LDO) designs in more advanced nodes such as for the 12nm FinFET process. Analog design is particularly challenging in FinFET processes due to a variety of factors, such as quantized parameters, large parasitic values and length of diffusion effects. An analog LDO was chosen for its improved power supply rejection ratio (PSRR) over digital and hybrid approach which is a key metric for voltage sensitive applications. The LDO was designed through an iterative approach to address the difficulty of designing analog devices in a FinFET node. The LDO has a good post layout line regulation of 0.57%/V, however a post layout has a load regulation of 4.9%/A. The LDO achieved a PSRR of -43dB at 100kHz and a noise value of 103 nV/√Hz at a current draw of 50mA and a layout size of 0.007225mm2. The PSRR is significantly better than comparable works that use a digital or hybrid LDO approach. The circuit had an overshoot value of 15mV, and a voltage undershoot value of 10mV when switching current by 100mA. In addition, the circuit was tested underneath multiple corners that would be used for automotive qualification from SS -40C to FF 125C with 13 corners total tested. The design was iterated to meet specifications on all corners. There are issues with the PSRR values and overshoot values at the SS -40C corner that are discussed. Potential fabrication of the circuit is also discussed.

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