Date of Graduation
5-2025
Document Type
Thesis
Degree Name
Master of Science in Mechanical Engineering (MSME)
Degree Level
Graduate
Department
Mechanical Engineering
Advisor/Mentor
Huitink, David
Committee Member
Peng, Yarui
Second Committee Member
Meng, Xiangbo
Keywords
Degradation; Electronic Packaging; Reliability; TIMs
Abstract
Power densities of electronic devices, specifically, integrated circuits (ICs) or chips, continue to rise significantly, generating considerable amounts of heat. These thermal load increases are detrimental to the performance and service life of chips within central processing units (CPUs) and graphics processing units (GPUs). These microprocessors are encompassed in electronic packages that provide several vital roles, most importantly heat removal. This is achieved by utilizing integrated heat spreaders and heat sinks that interact with various cooling architectures. However, surface deformities between components heavily limit the contact area for adequate heat transfer from the package. Thermal interface materials (TIMs) are incorporated into these high contact resistance regions, replacing non-conductive air gaps with conductive material that can conform to surface disparities. This improves the conduction thermal pathway and decreases abrupt temperature rises. However, TIMs experience extremely hostile conditions during their service life, deteriorating the thermal performance immensely and putting sensitive components at risk of failure. Numerous degradation trends have been observed in literature across a variety of TIMs, but only a handful of attempts at characterizing TIM degradation into predictive empirical models of thermal resistance. Furthermore, these predictive models were only subjected to thermal aging conditions or humidity stresses, with no models pertaining to stress conditions exhibited by processors. Additionally, the influence of TIM degradation on package reliability has not been explored in literature, potentially leading to overestimates of device lifetimes. In this thesis, a commercial TIM is subjected to power cycling conditions to replicate the thermo-mechanical stress conditions of a processor using a temperature difference (ΔT) of 75 °C and 85 °C, respectively. Quantifying the thermal resistance of the TIM was completed using a thermal circuit analysis and verified using steady-state thermal ANSYS simulations. Temperatures were measured using a thermocouple integrated into the heater placed on the TIM and an infrared camera that measured the temperature of the substrate underneath the TIM, with the substrate’s thermal resistance being accounted for in the thermal circuit analysis. The different stress conditions were plotted to analyze the degradation trends and develop a novel mathematical model to predict the thermal resistance of the TIM under power cycling conditions. Next, a methodology was established to examine the impacts of TIM degradation on the chip, specifically, its reliability, prognostics, and performance. The degradation models ascribed from literature were leveraged to emulate TIM degradation behaviors and applied to an electronic package frequently employed in server racks to develop critical relationships between electronic packages and TIM degradation.
Citation
Wagner, M. (2025). Development of a Degradation Methodology for Introducing Thermal Performance Deterioration of TIMs to Quantify Reliability Metrics of Electronic Packages. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/5754
