Describes a multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing VDD to both the first and second driver circuits. The first-rail logic circuit is coupled to VDD and ground, and has a first logic input and a first logic output. The second-rail logic circuit is coupled to VDD and ground, and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q1. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q0. The PMOS transistor has a gate driven by a SLEEP signal.
Electrical Engineering; Computer Science & Computer Engineering
Board of Trustees of the University of Arkansas (Little Rock, AR); NANOWATT DESIGN, LLC (Fayetteville, AR)
Smith, S. C., Di, J., Frenkil, J., Arthurs, A., & Foster, R. B. (2015). Single component sleep-convention logic (SCL) modules. Patents Granted. Retrieved from https://scholarworks.uark.edu/pat/4