Date of Graduation

5-2023

Document Type

Thesis

Degree Name

Master of Science in Materials Engineering (MS)

Degree Level

Graduate

Department

Materials Science & Engineering

Advisor/Mentor

Homer Alan Mantooth

Committee Member

Zhong Chen

Second Committee Member

Morgan E. Ware

Third Committee Member

Matthew Leftwich

Keywords

Drain engineering;Hot carrier effects;Low doped drain;Low voltage NMOSFET;SiC CMOS scaling;Submicron 4H-SiC

Abstract

Silicon carbide (SiC) is a wide semiconductor material with superior material properties compared to other rival materials. Due to its fewer dislocation defects than gallium nitride and its ability to form native oxides, this material possesses an advantage among wide band gap materials. Despite having several superior properties its low voltage application is less explored. CMOS is extremely important in low voltage areas and silicon is the dominant player in it for the last 50 years where scaling has contributed a major role in this flourishment. The channel length of silicon devices has reached 3 nm whereas SiC is still in the micrometer (2 μm/ 1.2 μm) range. So, SiC technology is still in its infancy which can be compared with silicon technology in the mid-1980s range. When the SiC devices would enter into the sub-micron and deep submicron range, proper device design in those ranges is necessary to rip the benefit of scaling. In this thesis, the SiC CMOS process available from different institutes and foundries is discussed first to understand the current state of the art. Later, low-voltage conventional SiC NMOS devices in the submicron range (2 μm to 600 nm) are simulated and their key parameters and performances are analyzed. In the submicron range, one major issue in MOSFET scaling is hot carrier effects. Thus to minimize this effect, a low-doped drain (LDD) region is introduced in the conventional SiC design having a channel length of 800 nm and 600 nm. In comparison with conventional designs, LDD designs have shown better saturation current behavior, reduced threshold roll-off, reduced hot electron current density, minimized gate leakage, reduced body hole current, enhanced voltage handling capability, reduced electric field, and improved subthreshold behavior in SiC. In the end, spacer technology, dopants, doping methods, and LDD realization technique in SiC are discussed.

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