Date of Graduation
12-2010
Document Type
Thesis
Degree Name
Master of Science in Computer Engineering (MSCmpE)
Degree Level
Graduate
Department
Computer Science & Computer Engineering
Advisor/Mentor
Jia Di
Committee Member
Dale R. Thompson
Second Committee Member
James P. Parkerson
Third Committee Member
Scott C. Smith
Keywords
2D to 3D conversion methodology, 3D chip design, Low power chip design, Multi-threshold cmos
Abstract
A new and exciting approach in digital IC design in order to accommodate the Moore's law is 3D chip stacking. Chip stacking offers more transistors per chip, reduced wire lengths, and increased memory access bandwidths. This thesis demonstrates that traditional 2D design flow can be adapted for 3D chip stacking. 3D chip stacking has a serious drawback: heat generation. Die-on-die architecture reduces exposed surface area for heat dissipation. In order to reduce heat generation, a low power technique named Multi-Threshold CMOS (MTCMOS) was incorporated in this work. MTCMOS required designing a power management unit (to control when and which gates are powered), a MTCMOS gate library, and a state saving D-Flip-Flop. This thesis demonstrates converting a traditional 2D chip to a low heat 3D chip design with the use of MTCMOS technology using industry-standard CAD tools.
Citation
Thian, R. J. (2010). Multi-threshold CMOS Circuit Design Methodology from 2D to 3D. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/52