Date of Graduation
5-2019
Document Type
Thesis
Degree Name
Master of Science in Computer Engineering (MSCmpE)
Degree Level
Graduate
Department
Computer Science & Computer Engineering
Advisor/Mentor
Jia Di
Committee Member
Jia Di
Second Committee Member
Dale R. Thompson
Third Committee Member
Patrick Parkerson
Keywords
Asynchronous, Circuit, Digital, MTNCL, Synthesis, VHDL
Abstract
As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.
Citation
Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/3168