Date of Graduation

12-2020

Document Type

Thesis

Degree Name

Master of Science in Mechanical Engineering (MSME)

Degree Level

Graduate

Department

Mechanical Engineering

Advisor

David Huitink

Committee Member

Wenchao Zhou

Second Committee Member

Yarui Peng

Keywords

Additive manufacturing, Integrated circuit interconnections, Power device reliability, Printed circuit board reliability, Semi Conductor packaging, Semi conductor reliability

Abstract

Semiconductor packaging and development is greatly dependent on the magnitude of interconnect and on-chip stress that ultimately limits the reliability of electronic components. Thermomechanical related strains occur because of the coefficient of thermal expansion mismatch from different conjoined materials being assembled to manufacture a device. To curb the effect of thermal expansion mismatch between conjoined parts, studies have been done in integrating compliant structures between dies, solder balls, and substrates. Initial studies have enabled the design and manufacturing of these structures using a photolithography approach which involves a high number of fabrication steps depending on the complexity of the structures and the masked approach may cause some structural alignment concerns during manufacturing. This research involves the fabrication of these structures using a different novel approach, utilizing additive manufacturing that reduces the number of fabrication steps required to obtain compliant geometries, eliminating the requirement for alignment tools, while also providing a platform for unique compliant structures. Additive manufacturing offers a solution to increasing fabrication concerns for electronics and additive manufacturing has emerged as a potential technology for improved customized and complex part fabrication. This thesis provides a review of common additive manufacturing approaches ranging from material development, process fabrication development, and applications that have been demonstrated in the electronics industry whilst also eliminating non critical process such as masking concerns, depending on geometry size. This thesis discusses two main methods of fabrication and analyzes the properties and effects of these interconnect structures on a die. Structural finite element thermal cycling simulations between -40 to 125oC show about a 115% increase in the solder joint fatigue life. Additionally, fabricated test structures created directly on a PCB were experimentally characterized for compliance using a micro-indenter tester, showing a mechanical compliance range of 265.95 to 656.78 µm/N for selected design parameters to be integrated into a test vehicle. This approach can accomplish similar thermomechanical stress alleviation to formerly reported methods, but with fewer process steps, and potential for new geometry manufacturing. Further validation of the finite element reliability has been done by integrating an in situ elevated temperature shear stress study. The compliant interconnect packaged device demonstrated enhanced electrical reliability performance when compared with the package without the interconnects.

Available for download on Tuesday, August 17, 2021

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