Date of Graduation

12-2022

Document Type

Thesis

Degree Name

Master of Science in Computer Engineering (MSCmpE)

Degree Level

Graduate

Department

Computer Science & Computer Engineering

Advisor/Mentor

Jia Di

Committee Member

Dale Thompson

Second Committee Member

Brajendra Panda

Keywords

Asynchronous, Fast Fourier Transform

Abstract

Fast Fourier Transform (FFT) is a widely used digital signal processing technology in a large variety of applications. For battery-powered embedded systems incorporating FFT, its physical implementation is constrained by strict power consumption, especially during idle periods. Compared to the prevailing clocked synchronous counterpart, quasi-delay insensitive asynchronous circuits offer a series of advantages including flexible timing requirement and lower leakage power, making them ideal choices for these systems. In this thesis work, various FFT configurations were implemented in the low-power Multi-Threshold NULL Convention Logic (MTNCL) paradigm. Analysis illustrates the area and power consumption trends along the changing of the number of points, data widths, and the number of pipeline stages.

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