Date of Graduation
8-2013
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
Degree Level
Graduate
Department
Electrical Engineering
Advisor
Scott C. Smith
Committee Member
Randy Brown
Second Committee Member
Alan Mantooth
Third Committee Member
Jia Di
Keywords
Applied sciences, Asynchronous circuits, Bit-wise ncl, Bolean to mtncl, Cad tool design, Mtncl, Ncl
Abstract
This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and Synopsis CAD tools, using a C-program, which performs the majority of the computations, such that the method can be easily ported to other CAD tool suites. Both methods have been successfully tested on circuits, including a 4-bit × 4-bit multiplier, an unsigned Booth2 multiplier, and a 4-bit/8-operation arithmetic logic unit (ALU)
Citation
Pillai, V. M. (2013). CAD Tool Design for NCL and MTNCL Asynchronous Circuits. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/829