Describes a hybrid digital-analog computer parallel processing apparatus wherein a template circuit, or multiplicity thereof, is connected to receive parallel digital inputs. Each template circuit has controlled current sources with control gates connected respectively to parallel digital inputs. Current subsources for each pixel normally have programmable current output and “0” or “1” responses. Each template circuit has a current summing device for algebraically adding the current outputs of current sources, while a greatest value is detected at a comparator which may have a ramp signal applied to another input thereby identifying which template produced a maximum indication from the same parallel inputs. A self-calibrating feedback controlled current generator supplies all current sources on a chip making it possible to generate a known comparator input independent of IC resistivity or other parameters. The value of the indication of other templates may also be determined by the time relation of comparator output signals. If templates of the apparatus represent printed character correlation data, the output of the processor would identify the template with maximum indication and character with highest probability from a set of pixel inputs. Similar apparatus can be cascaded to first identify details in a scene and then match such detail charts with second stage templates.
Computer Science & Computer Engineering; Electrical Engineering
University of Arkansas (Little Rock, AR)
Bass, J. E., & Brown, R. L. (1992). Hybrid digital-analog computer parallel processor. Patents Granted. Retrieved from https://scholarworks.uark.edu/pat/240
J. E. Bass, Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR
Randy L. Brown, Department of Electrical Engineering, University of Arkansas, Fayetteville, AR