Document Type

Patent

Publication Date

7-12-2011

Abstract

A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) is described. The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Department

Computer Science and Computer Engineering; Electrical Engineering

Patent Number

US7977972

Application Number

US20110032000

Application Published

2-10-2011

Application Filed

4-30-2010

Assignee

Board of Trustees of the University of Arkansas (Little Rock, AR)

Comments

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under W15P7T-08-C-V404 awarded by the DARPA Microsystems Technology Office. The government has certain rights in the invention.

Jia Di, Department of Computer Science and Computer Engineering

Scott C. Smith, Department of Electrical Engineering

Share

COinS