A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) is described. The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
Computer Science and Computer Engineering; Electrical Engineering
Board of Trustees of the University of Arkansas (Little Rock, AR)
Di, J., & Smith, S. C. (2011). Ultra-low power multi-threshold asynchronous circuit design. Patents Granted. Retrieved from https://scholarworks.uark.edu/pat/67