Date of Graduation
Master of Science in Computer Engineering (MSCmpE)
Computer Science & Computer Engineering
Second Committee Member
The computer industry's transition to multiprocessor systems on chip (MPSoC) architectures is increasing the need for new scalable high-bandwidth on-chip communication
backbones. Network-on-Chip (NoC) interconnects are gaining interest for serving as the on-chip communication infrastructure. The most important issues to be considered in designing a NoC are topology, routing algorithm, flow control, and buffering and also the trade-offs between performance, power, and area.
This research proposes a custom-designed NoC specifically for MPSoCs on FPGAs. The proposed design allows the communication infrastructure to seamlessly scale as the numbers of processors within the chip increases. The design adds a new level of abstraction to remote-access transactions. The design also considers support for the
partitioned global address space model with support for optional embedded local memories embedded in the network interface. The network was designed as a mesh topology to allow a reasonable communication capacity in 2-Dimensional space. The communication protocol between source and destination is AMBA AXI4, and the communication between each two adjacent nodes, is typical AXI type valid/ready handshake. The nodes are distinguished by their user specified address range. Each node is assigned a range of addresses, and in each transaction, based on the destination address, the routers decide the the next node, until the transaction reaches the
destination. The design has been implemented on a Xilinx Virtex7 FPGA. However, there is no platform dependency to any brand or any model of FPGAs.
%In the first chapter in this research, we give an introduction of the work. In chapter 2, we talk about the background of MPSoCs and interconnections. We discuss the AXI protocl, and then we specifically talk about different Network-on-Chip projects. In chapter 3, we describe the design details for different component an also the high level design of the system, we also, discuss the implementation details of the design. In chapter 4, we show the experimental results for both verification phase and the analysis of the system. Finally, chapter 5 concludes the research.
Fakhari, A. (2014). Designing Customizable Network-on-Chip with support for Embedded Private Memory for Multi-Processor System-on-Chips. Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/1058