Date of Graduation
8-2012
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Engineering (PhD)
Degree Level
Graduate
Department
Electrical Engineering
Advisor/Mentor
Scott C. Smith
Committee Member
Jia Di
Second Committee Member
Alan Mantooth
Third Committee Member
Randy Brown
Fourth Committee Member
Simon Ang
Keywords
Applied sciences, Asynchronous design, Carbon nanotubes, Digital circuits, Digital design, Ternary logic, Transistors
Abstract
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures require substantially less power, generate less noise, and produce less electromagnetic interference (EMI). This dissertation develops the Delay Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines the designs aspects of similar Dual-Rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme.
DITL is designed at the transistor level using multi-threshold CMOS and carbon nanotube (CNT) FETs to develop primitive logic gates, which are combined to design larger circuits, simulated at the transistor level, and compared with other paradigms for energy, timing, and area. DITL is applied to design secure hardware resistant to side-channel attacks and found to be more attack resistant than other methods.
Citation
Parameswaran Nair, R. (2012). Delay Insensitive Ternary Logic Utilizing CMOS and CNTFET. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/548
Included in
Electrical and Electronics Commons, Electronic Devices and Semiconductor Manufacturing Commons, VLSI and Circuits, Embedded and Hardware Systems Commons