Title

ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks

Document Type

Article

Publication Date

2015

Keywords

Hardware, Electronic design automation, High-level and register-transfer level synthesis

Abstract

A synthesis approach based on Answer Set Programming (ASP) for heterogeneous system-on-chips to be used in distributed camera networks is presented. In such networks, the tight resource limitations represent a major challenge for application development. Starting with a high-level description of applications, the physical constraints of the target devices, and the specification of network configuration, our goal is to produce optimal computing infrastructures made of a combination of hardware and software components for each node of the network. Optimization aims at maximizing speed while minimizing chip area and power consumption. Additionally, by performing the architecture synthesis simultaneously for all cameras in the network, we are able to minimize the overall utilization of communication resources and consequently reduce power consumption. Because of its reconfiguration capabilities, a Field Programmable Gate Array (FPGA) has been chosen as the target device, which enhances the exploration of several design alternatives. We present several realistic network scenarios to evaluate and validate the proposed synthesis approach.

Comments

Principal Investigator: Cristophe Bobda This work is supported by the National Science Foundation under grant CNS-1302596. This work is supported by the National Science Foundation under grant CNS-1302596.

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