Date of Graduation
Bachelor of Science in Computer Engineering
Computer Science and Computer Engineering
Committee Member/Second Reader
The SPAR-2 array processor was designed as an overlay architecture for implementation on Xilinx Field Programmable Gate Arrays (FPGAs). As an overlay, the SPAR-2 array processor can be configured to take advantage of the specific resources available on different FPGAs. However once configured, the SPAR-2 requires programmer’s to have knowledge of the low level architecture, and write platform-specific code. In this thesis SVAR, a hardware/software co-designed virtual machine, is proposed that runs on the SPAR-2. SVAR allows programmers to write portable, platform-independent code once and have it interpreted for any specific configuration. Results are presented that verify the virtual machine enables the same code to run without modification on different configurations of the SPAR-2 array running on different FPGA platforms. The results show that the performance cost of this portability is modest, incurring an average 5.6% decrease in performance in partial MLP simulations compared to hand-tuned custom code.
Virtual Machine, Array Processor, Portable code, SPAR, FPGA, Reconfigurable
Fredricks, N. (2023). SVAR: A Virtual Machine for Portable Code on Reconfigurable Accelerators. Computer Science and Computer Engineering Undergraduate Honors Theses Retrieved from https://scholarworks.uark.edu/csceuht/119