Date of Graduation
Bachelor of Science in Computer Engineering
Computer Science and Computer Engineering
Committee Member/Second Reader
Digital integrated circuits (ICs) have become progressively complex in their functionality. This has sped up the demand for asynchronous architectures, which operate without any clocking scheme, considering new challenges in the timing of synchronous systems. Asynchronous ICs have less stringent environmental constraints and are capable of maintaining reliable operation in extreme environments, while also enjoying potential benefits such as low power consumption, high modularity, and improved performance. However, when the traditional bus architecture of synchronous systems is applied to asynchronous designs, handshaking protocols required for asynchronous circuit operation result in significantly increased power consumption, offsetting the low power benefit of asynchronous designs. In this thesis, NULL Convention Logic is used to implement two data transfer alternatives to the bus, and their performance is compared to that of the prevailing bus architecture. According to the results, both of these proposed architectures demonstrate power-saving qualities while sacrificing area, indicating potential utilization in power-constrained applications where speed is not a prioritized design constraint, as in Internet of Things (IoT) devices.
Asynchronous, Low-power, communication, bus
Howard, M. (2018). Comparison of Data Transfer Alternatives in Asynchronous Circuits. Computer Science and Computer Engineering Undergraduate Honors Theses Retrieved from https://scholarworks.uark.edu/csceuht/51