Date of Graduation
5-2014
Document Type
Thesis
Degree Name
Master of Science in Computer Engineering (MSCmpE)
Degree Level
Graduate
Department
Computer Science & Computer Engineering
Advisor/Mentor
Di, Jia
Committee Member
Parkerson, James P.
Second Committee Member
Thompson, Dale R.
Keywords
Asynchronous; Radiation Hardening; SEL Protection; SEU Mitigation
Abstract
Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss.
Citation
Brady, J. D. (2014). Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/2299
