Date of Graduation

12-2019

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Computer Science & Computer Engineering

Advisor/Mentor

Di, Jia

Committee Member

Parkerson, James P.

Second Committee Member

Thompson, Dale R.

Third Committee Member

Wu, Jingxian

Keywords

Asynchronous Energy Consumption; Asynchronous IC Design; Asynchronous Power Consumption; NULL Convention Logic; Static Power Consumption; Voltage Scaling

Abstract

Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.

While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm.

This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in circuit type, circuit scale, and technology node, including 130 nm, 90 nm, and 45 nm processes. These results are compared with synchronous counterparts and analyzed for a range of trends in order to identify and quantify advantages and disadvantages of NCL across a variety of applications. By providing an evaluation of a broad range of circuits and characteristics, an IC designer may effectively predict the advantages or disadvantages of an NCL implementation for their application.

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