Date of Graduation

5-2020

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Electrical Engineering

Advisor/Mentor

Smith, Scott C.

Committee Member

Di, Jia

Second Committee Member

Mantooth, H. Alan

Third Committee Member

Wu, Jingxian

Keywords

Asynchronous logic; Built-in self-test (BIST); Multi-Threshold NULL Convention Logic (MTNCL); NULL Convention Logic (NCL); Sleep Convention Logic (SCL)

Abstract

This dissertation proposes a Built-In Self-Test (BIST) hardware implementation for Multi-Threshold NULL Convention Logic (MTNCL) circuits. Two different methods are proposed: an area-optimized topology that requires minimal area overhead, and a test-performance-optimized topology that utilizes parallelism and internal hardware to reduce the overall test time through additional controllability points. Furthermore, an automated software flow is proposed to insert, simulate, and analyze an input MTNCL netlist to obtain a desired fault coverage, if possible, through iterative digital and fault simulations. The proposed automated flow is capable of producing both area-optimized and test-performance-optimized BIST circuits and scripts for digital and fault simulation using commercial software that may be utilized to manually verify or adjust further, if desired.

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