Date of Graduation

7-2020

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Electrical Engineering

Advisor/Mentor

Luo, Fang

Committee Member

Balda, Juan C.

Second Committee Member

Zhao, Yue

Third Committee Member

Huitink, David

Keywords

hybrid switch; power module; module operating voltage; stacking; parasitic interconnect

Abstract

Advancements in the converter- and module-level packaging will be the key for the development of the emerging high-power, high power-density, high-eciency power conversion applications, such as traction, shipboards, more-electric-aircraft, and locomotive. Wide bandgap (WBG) devices such as silicon carbide (SiC) MOSFET attract much attention in these applications for their fast switching speeds, resulting in low loss and a consequent possibility for high switching frequency to increase the power density. However, for high-current, high power implementations, WBG devices are still available in small die sizes. Multiple SiC devices need to be connected in parallel to replace a large IGBT die. It is challenging to realize high-switching-frequency and low loss with a lot of parallel devices due to the inherent parameter dierences, which lead to unbalanced dynamic current sharing resulting in unequal temperature distribution and overstress. Apart from the technical challenges, the price of SiC modules is another roadblock for its widespread application. The paralleling of a large number of SiC chips in the module to handle high current increases the module cost. Hence, this work proposes a Si-IGBT and SiC-MOSFET-based hybrid switch solution. For a converter-level packaging, the device technology, available device package, and orientation of the pins are the essential governing factors. This work addresses the converter-level packaging, which is referred to as a power electronics building block, of the proposed hybrid switch, combining discrete packages and frame-based modules for the devices and a singlephase three-level T-type topology. The primary optimization objective for converter-level packaging includes low inductance busbar design, high eciency, and high specic and volumetric power density. Overall implementation is not trivial; however, this work achieves an optimum design compared to the state-of-the-art. The module-level packaging challenges are dependent on the type of device technology and topology. Reducing the parasitic inductances, capacitances, and the junction to case thermal resistance are the optimization objectives in module packaging. Given the intended application of the module, achieving a high-reliability module is also essential. This work includes a hybrid switch-based power module addressing the challenges of WBG module-level packaging and challenges specic to the hybrid switch. The availability of engineering samples of SiC MOSFETs with voltage ratings above 10 kV and commercialization in the future drive the module-level packaging of high voltage devices. High voltage power modules will support the development of future solid-state circuit breakers, transformers, and power conversion applications in shipboards and rolling stocks. The availability of these modules can eliminate the necessity of multilevel topologies. This work investigates and demonstrates the module-level packaging of HV (10-15 kV) SiC MOSFETs.

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