Date of Graduation

12-2021

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Mechanical Engineering

Advisor/Mentor

David R. Huitink

Committee Member

David C. Jensen

Second Committee Member

Paul Milllett

Third Committee Member

Yarui Peng

Keywords

Electronic industry, Reliability, low cycle fatigue

Abstract

The trend toward miniaturization of electronic devices to fulfill Moore’s law introduces new reliability concerns to the electronic packaging process while worsening existing primary challenges. In solder interconnect specifically, temperature cycling is one of the prominent failure threats. However, with further downscaling of the flip-chip solder connections, electromigration also present a precarious failure mode in these interconnects. On the other hand, understanding the degradation mechanism in solders is crucial for the power electronic products' reliability considering the industrial tendency to replace wirebonds with solder attachment while improving the current carry capacity. This dissertation utilizes FEA simulation and an experimental approach to study the solder’s reliability. First, the SiC MOSFET packaging method using flip-chip technology has been studied to achieve an optimum arrangement that improves reliability and electrical characteristics. Also, the opportunity to estimate the flip-chipped package thermal cycling reliability using mechanical cycling as a fast reliability estimation tool is investigated, and the related Norris-Landsberg parameters are calculated using the FEA approach. Lastly, a testing setup has been developed to study the combined effects of electromigration and stress in solder connection. The MTTF of the joint under tensile stress, while it is experiencing current stressing, is measured. This work can guide further experimental and computational works to identify the degradation in the solders under multiple environmental and operational conditions.

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