Date of Graduation

12-2022

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Electrical Engineering

Advisor/Mentor

H. Alan Mantooth

Committee Member

Yarui Peng

Second Committee Member

Wing Ning Li

Third Committee Member

Yue Zhao

Keywords

MCPM, PowerSynth

Abstract

In recent years, the fast development of Multichip Power Modules (MCPM) packaging and Wide Bandgap (WBG) technology has enabled higher voltage and current ratings, better thermal performance, lower parasitic parameters, and higher mechanical reliability. However, the design of the MCPM layout is a multidisciplinary problem leading to many time-consuming analyses and tedious design processes. Because of these challenges, the design automation tool for MCPM layout has become an emerging research area and gained much attention from the power electronics community. The two critical objectives of a design automation tool for MCPM layout are fast and accurate models for design insights and a feasible layout generation algorithm for quick transition to hardware fabrication. On this end, PowerSynth, the MCPM design automation tool, has met these two key factors and become one of the most mature tools in the design automation community. Along with a generic and constraint-aware layout generation algorithm, the PowerSynth model library allows fast design insights on thermal performance, electrical parasitic extraction, mechanical reliability, and design rules for partial discharge. This diversity in modeling and layout algorithms has opened many challenges to enhance the tool capabilities further.The focus of this work is the modeling and extraction of electrical parasitic parameters within the MCPM design automation scope. This topic has been previously approached by adopting microstrip models combined with Laplacian Matrix evaluation for fast electrical parasitic evaluation. However, the two critical limitations of this approach are inaccurate parasitic models for some Direct Bonded Copper (DBC) substrates and a lack of mutual coupling consideration among different conducting paths. In the first part of this work, response surface modeling has been used to replace the inaccurate microstrip equations, while methodologies such as Partial Element Equivalent Circuit (PEEC) and Loop-based methods are used to consider mutual coupling. This combination ensures fast and accurate design insights during the MCPM layout optimization process. In previous studies, PowerSynth commonly produced electrically optimized layouts by reducing their power loop inductance. While this approach effectively reduces the overshoot voltage, it lacks crucial information about other dynamic performance criteria. Hence, in the second part of this work, a methodology has been developed to allow the optimization tool to assess a more electrically optimized layout in terms of overall dynamic performance.

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