Date of Graduation
8-2012
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
Degree Level
Graduate
Department
Electrical Engineering
Advisor/Mentor
Smith, Scott C.
Committee Member
Di, Jia
Second Committee Member
Brown, Randy L.
Keywords
Applied sciences; Arithmetic Logic Unit; Pipeline; Sleep convention logic
Abstract
This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both nsleep and sleep signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.
Citation
Zhao, J. (2012). Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/552
