Date of Graduation
9-2025
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
Degree Level
Graduate
Department
Electrical Engineering and Computer Science
Advisor/Mentor
Dix, Jeff
Committee Member
Alan Mantooth
Second Committee Member
Jia Di
Abstract
The advent of large language models [1] brought awareness to the importance of advances in high-performance computing and neural network algorithm design. These systems rely upon highly networked accelerator ASICs made on advanced nodes such as TSMC 4N, with NVIDA’s H100 having 80 billion transistors on-die [2]. However, the millions of parameters needed to arrive at satisfactory performance require massive parallelization of processing. This demands high-throughput networking, both from chip-to-chip and rack-to-rack. Currently, x86-type servers use 5-6 Ethernet switch ports per server, while typical AI/ML servers need 12+ ports [20]. Often, memory access and networking throughput can limit the overall performance of the system. Serializer/de-serializer (serDes) electrical and optical links are the primary way data is moved at high volume between these devices. Time-interleaved data converter-based receivers with digital equalization have led to electrical links with speeds up to 220Gb/s [3]. As this thesis will demonstrate via system modeling, they are robust over a higher channel loss. These receivers are implemented on highly scaled CMOS nodes of the accelerators. CMOS nodes below and at 28nm offer a unique set of design trade-offs when compared to long-channel CMOS. The design of mixed-signal circuits can make use of fast, efficient digital signal processing to reduce the performance requirements of analog circuits. On the other hand, a low supply voltage makes traditional linear amplification techniques challenging. Due to these constraints, the serial approximation register ADC has become advantageous, since it primarily consists of switches, latches, and capacitors, which all scale well in nanometer CMOS, however, this scaling does not include linear amplification. Serial approximation register (SAR) ADCs are well-suited to medium precision and medium speed applications, and have a high power efficiency. For these reasons, power and area-efficient SAR ADCs that can be arrayed easily for time-interleaving are of high interest.
Citation
Venker, J. S. (2025). Time-Interleaved SAR ADC in 22nm FD-SOI CMOS. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/5840
