Date of Graduation
5-2026
Document Type
Thesis
Degree Name
Master of Science in Computer Engineering (MSCmpE)
Degree Level
Graduate
Department
Computer Science & Computer Engineering
Advisor/Mentor
Di, Jia
Committee Member
Andrews, David
Second Committee Member
Dix, Jeff
Keywords
Asynchronous; MTNCL; Ternary
Abstract
Asynchronous circuit design paradigms, such as NULL convention logic (NCL) and Multi-Threshold NCL (MTNCL), offer increased energy efficiency over synchronous equivalents and robust pipelines with minimal timing analysis. However, their dependency on dual-rail signal encoding causes significant overhead compared to single-rail equivalents. Previous single-gate and single-rail NCL paradigms have sought to reduce circuit area, but most compromise their quasi-delay-insensitivity and correct-by-construction nature with logic gate and system-level design choices. This thesis presents Single-Gate MTNCL (SG-MTNCL), a register controlled, single-gate, and dual-rail asynchronous architecture to improve the area efficiency of MTNCL without compromising the reliability of previous paradigms. The benefits of the SG-MTNCL paradigm were validated in the TSMC 65nm process. In addition to individual logic gate design, a dense layer cell from a Recurrent Neural Network (RNN) was implemented. Ultimately, the data in this thesis demonstrates through physical design that the SG-MTNCL paradigm is a viable approach for designing asynchronous circuits that are more area efficient than traditional MTNCL
Citation
Swaim, J. E. (2026). Design and Evaluation of a Single-Gate Multi-Threshold NULL Convention Logic Architecture for Area Efficiency. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/6128
