Date of Graduation

5-2026

Document Type

Dissertation

Degree Name

Doctor of Philosophy in Engineering (PhD)

Degree Level

Graduate

Department

Computer Science & Computer Engineering

Advisor/Mentor

Di, Jia

Committee Member

Nelson, Alexander

Second Committee Member

Thompson, Dale

Third Committee Member

Dix, Jeff

Keywords

Asynchronous Polymorphic Logic Locking (APLL); polymorphic logic; Multi-Threshold NULL Convention logic (MTNCL)

Abstract

This work presents Asynchronous Polymorphic Logic Locking (APLL), a logic locking methodology that integrates polymorphic logic within the Multi-Threshold NULL Convention Logic (MTNCL) paradigm. APLL achieves Boolean satisfiability-attack resilience through a fault-based logic stripping approach followed by logic restoration, while leveraging the analog, dual-functionality of polymorphic gates to impede reverse engineering and removal attacks. In contrast to comparable SAT-resistant logic locking techniques, APLL provides inherent resistance to reverse engineering, reducing the viability of a broad class of attacks that rely on access to the locked netlist. A complete automated design flow is developed, enabling the transformation of combinational circuits into locked gate-level MTNCL polymorphic implementations. Experimental evaluation across multiple benchmark circuits demonstrates that APLL provides strong resistance to SAT attacks, with exponential increases in execution time observed as the key size increases. Additionally, APLL exhibits resilience to structural attacks, and practical feasibility is maintained through optional integration of Fault-based Logic Locking (FLL), a high-corruption primitive locking technique. Following physical implementation in the GlobalFoundries 12LP FinFET technology and parasitic extraction, transistor-level simulations were performed to evaluate overhead. Results indicate tradeoffs between security and performance, with power and area overhead scaling favorably as circuit size increases.

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