Date of Graduation
12-2012
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Engineering (PhD)
Degree Level
Graduate
Department
Computer Science & Computer Engineering
Advisor/Mentor
Di, Jia
Committee Member
Mantooth, H. Alan
Second Committee Member
Smith, Scott C.
Third Committee Member
Parkerson, James P.
Keywords
Applied sciences; Adaptive asynchronous architecture; Asynchronous; Digital; Energy efficiency; Ncl
Abstract
Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach.
Citation
Hollosi, B. M. (2012). Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/654
Included in
Electrical and Electronics Commons, Systems and Communications Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
