Date of Graduation
5-2013
Document Type
Dissertation
Degree Name
Doctor of Philosophy in Engineering (PhD)
Degree Level
Graduate
Department
Electrical Engineering
Advisor/Mentor
Smith, Scott C.
Committee Member
Di, Jia
Second Committee Member
Mantooth, H. Alan
Third Committee Member
Wu, Jingxian
Keywords
Applied sciences; ASIC; Asynchronous logic; Low-power; Sleep convention logic
Abstract
This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.
Citation
Palangpour, P. (2013). CAD Tools for Synthesis of Sleep Convention Logic. Graduate Theses and Dissertations Retrieved from https://scholarworks.uark.edu/etd/755
