Document Type

Patent

Publication Date

1-18-2005

Abstract

A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer is described. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1x10^20 dopant atoms per cubic cm of silicon.

Department

Electrical Engineering

Patent Number

US6844248

Application Number

US20040106227

Application Published

6-3-2004

Application Filed

7-14-2003

Assignee

Board of Trustees of the University of Arkansas (Little Rock, AR)

Comments

Hameed A. Naseem, Department of Electrical Engineering, University of Arkansas, Fayetteville, AR
M. Shahidul Haque, Department of Electrical Engineering, University of Arkansas, Fayetteville, AR
William D. Brown, Department of Electrical Engineering, University of Arkansas, Fayetteville, AR

Share

COinS