Document Type
Patent
Publication Date
8-17-2021
Abstract
A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.
Department
Electrical Engineering
Patent Number
US11094690
Application Number
US 20200098742 A1
Application Published
3-26-2020
Application Filed
9-24-2019
Assignee
Board of Trustees of the University of Arkansas (Fayetteville, AR)
Citation
Chen, Z., & Farbiz, F. (2021). On-chip IEC ESD protection using parasitic PNP devices. Patents Granted. Retrieved from https://scholarworks.uark.edu/pat/404
COinS
Comments
Zhong Chen, Department of Electrical Engineering, University of Arkansas, Fayetteville, AR