Document Type
Article
Publication Date
10-26-2025
Abstract
This paper presents a radiation-hardened 4-bit flash analog-to-digital converter (ADC) implemented in a 22 nm fully depleted silicon-on-insulator (FD-SOI) process for high-reliability applications in radiation environments. To improve single-event upsets (SEU) tolerance, the design introduces a compact fault-tolerant logic scheme based on Dual Modular Redundancy (DMR), offering reliability comparable to Triple Modular Redundancy (TMR) while using two storage nodes instead of three, and a simple XOR-based check in place of a majority voter. A distributed sampling architecture mitigates SEU vulnerabilities in the input path, while thin-oxide devices are used in analog-critical circuits to enhance total ionizing dose (TID) resilience. Post-layout simulations demonstrate SEU detection within 200 ps and correction within ~600 ps. The ADC achieves an active area of 0.089 mm2, power consumption below 30 µW, and provides a scalable solution for radiation-tolerant data acquisition in aerospace and other high-reliability systems.
Citation
Naveed, F., & Dix, J. (2025). A Radiation-Hardened 4-Bit Flash ADC with Compact Fault-Tolerant Logic for SEU Mitigation. Electronics, 14 (21) https://doi.org/https://doi.org/10.3390/electronics14214176
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Keywords
flash ADC, FD-SOI, single-event upsets (SEUs), total ionizing dose (TID), dual modular redundancy (DMR), radiation-hardened circuits, error detection and correction
Comments
Web of Science
MDPI