SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs

Author

Peter Tucker, University of Arkansas, Fayetteville

Date of Graduation

5-2013

Document Type

Thesis

Degree Name

Bachelor of Science

Degree Level

Undergraduate

Department

Electrical Engineering

Advisor/Mentor

Mantooth, H. Alan

Abstract

Multi-Chip Power Module (MCPM) designs are widely used in the area of power electronics to control multiple power semiconductor devices in a single package. The work described in this thesis is part of a larger ongoing project aimed at designing and implementing a computer aided drafting tool to assist in analysis and optimization of MCPM designs. This thesis work adds to the software tool the ability to export an electrical parasitic model of a power module layout into a SPICE format that can be run through an external SPICE circuit simulator. The code was implemented in python using NetworkX graphs to build parasitic circuit models and then write a netlist that can be interpreted by SPICE. Upon completion of the code, sample layouts were exported to netlists and run through circuit simulations using Synopsys® HSpice. An example simulation result is shown in this thesis and compared to an ideal case and a high parasitic case.

Citation

Tucker, P. (2013). SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs. Electrical Engineering Undergraduate Honors Theses Retrieved from https://scholarworks.uark.edu/eleguht/4